The present invention relates in general to semiconductor technology, and more particularly to methods and structures for three-dimensional (3D) stacked semiconductor devices. Merely by way of example, the invention has been applied to forming 3D stacked semiconductor devices incorporating two or more trench field effect transistors (FETs). But it would be recognized that the invention has a much broader range of applicability.
High voltage and/or high power devices are finding increasingly broad applications in modern electronics. For example, these devices are used in applications such as portable consumer electronics, power management circuits, automotive electronics, disk drives, display devices, RF communication circuits, and wireless base station circuits. Some of the power devices include shielded gate trench FETs and trench gate FETs. An example is briefly discussed below.
FIG. 1 is a simplified cross sectional view diagram of a shielded gate trench MOSFET. An n-type epitaxial layer 102 extends over n+ substrate 101. N+ source regions 108 and p+ heavy body regions 106 are formed in a p-type body region 104, which is in turn formed in epitaxial layer 102. Trench 110 extends through body region 104 and terminates in the drift region which is the portion of epitaxial layer 102 extending between body region 104 and substrate 101. Trench 110 includes a shield electrode 114 below a gate electrode 122. Gate electrode 122 is insulated from its adjacent silicon regions by gate dielectric 120, and shield electrode 114 is insulated from adjacent silicon regions by a shield dielectric 112 which is thicker than gate dielectric 120. The gate and shield electrodes are insulated from each other by a dielectric layer 116 also referred to as inter-electrode dielectric or IED.
The structure of FIG. 1 can be repeated many times to form an array of transistors. FIG. 2 is a simplified cross-sectional view diagram illustrating a portion of a trench MOSFET 200, which includes substrate 201, epitaxial layer 202, and body region 204. Device 200 also includes an array of trench cells 206 linked together in parallel. Each of trench cell 206 is similar to the shielded gate FET of FIG. 1. Conductive region 214, which is protected by dielectric layer 226, is the gate electrode of MOSFET 200, and is connected to the gate electrode in each trench cell. Contact to the drain region can be made on the back side of the device. Contacts to the source metal can be made on the top surface of the device, whereas contacts to the gate electrode can be made in an edge portion of the top surface.
In power electronics applications, the demand for higher performance and lower cost continues to increase. On the other hand, as power device technology advances, it becomes increasing difficult to improve the performance. For example, scaling down cell dimension requires complicated processing. Additionally, as the device area is reduced, the power handling capacity may suffer. These and other limitations pose great challenges to further improvement of power devices.
Thus, there is a need for improved structures and methods for forming high-performance, low cost power devices.